URC97020 Off-Line Testing for Bridge Faults in CMOS Domino Logic Circuits
نویسندگان
چکیده
Bridge faults, especially in CMOS circuits, have unique characteristics which make them difficult to detect during testing. This paper presents a technique for detecting bridge faults which have an effect on the output of CMOS Domino logic circuits. The faults are modeled at the transistor leveI and .lhis technique is based on analyzing the off-set of the function during off-line testing.
منابع مشابه
Physical design for testability for bridges in CMOS circuits
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